1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to improvement of the reliability thereof in a temperature cycle test.
2. Description of Related Art
A temperature cycle test is conventionally imposed as one type of reliability evaluation test on semiconductor integrated circuit devices in which high reliability is required in varying use environments (e.g., a serial control LED (light emitting diode) driver for automobiles). A temperature cycle test is a test in which a semiconductor integrated circuit device is tested for reliability by being exposed alternately to a high and a low temperature (e.g., +150° C. and −65° C.) repeatedly at predetermined intervals.
When a conventional semiconductor integrated circuit device is subjected to the temperature cycle test as described above, thermal stress resulting from differences in thermal expansion coefficient among an element forming region, a metal wiring layer, and a passivation layer may produce a crack (exfoliation) in the passivation layer, causing even the metal wiring layer right under the passivation layer to exfoliate together in the worst case. This leads to degraded reliability and reduced yields. In particular, elongate chips such as display drivers and sensors are liable to be seriously affected.
As a solution to the above described problem, a semiconductor integrated circuit device has conventionally been disclosed and proposed in which a metal wiring layer and a passivation layer have elevations and depressions (slits) formed thereon (see JP-A-H05-283540, hereinafter referred to as Patent Literature 1).
As another conventional art related to the present invention, a semiconductor chip in which a dummy pattern is formed between an identification area including an identification mark and a dicing line has been disclosed and proposed (see JP-A-H05-251556 filed by the applicant of the present application, hereinafter referred to as Patent Literature 2).
With the conventional art of Patent Literature 1, it is indeed possible to disperse thermal stress to prevent development of cracks in the passivation layer. However, the conventional art of Patent Literature 1 is disadvantageous in that it requires an extra process for forming elevations and depressions on the metal wiring layer and the passivation layer (more specifically, a process for forming elevations and depressions on an interlayer insulating film laid immediately under the metal wiring layer), and this invites reduced productivity and yields.
The conventional art of Patent Literature 2 simply aims at reducing exfoliation during the dicing of a semiconductor chip and the resulting identification errors. Thus, it in no way helps prevent development of cracks in a passivation layer during a temperature cycle test.